1. Field of the Invention
The invention relates to a semiconductor memory device having floating gate transistors which are used for holding data such as redundance replacement addresses, a device initial state and the like.
2. Description of the Related Art
In a large capacity memory device, replacement of defective memory cells is conducted using a redundant circuit, as means for relieving the device from failures due to defects of memory cells. Such a redundant circuit includes reserved memory cells which, when there exist defective memory cells, are to substitute for the defective memory cells, and a circuit which stores the addresses of the defective memory cells (hereinafter, referred to as "defective addresses") and replaces the defective memory cells with the reserved memory cells. Generally, one of the following two methods is employed as a method of storing such defective addresses, depending on types of devices.
In a volatile memory device such as a DRAM or an SRAM, employed is a method in which a plurality of fuses formed by polysilicon or a metal are arranged in the device and the fuses are selectively disconnected by electrical means, a laser beam or the like, thereby storing defective addresses. On the other hand, in an EPROM or a flash memory, defective addresses are stored by using the memory cells in place of fuses, since such memory cells themselves are nonvolatile.
The aforementioned methods are also applicable to a memory element which is used for storing the initial state of a device.
FIG. 7 is a circuit diagram of an exemplary conventional redundant defective address memory circuit which is used in a conventional EPROM or flash memory. The memory circuit is described in detail in U.S. Pat. No. 5,267,213.
In FIG. 7, a CAM (Contents Addressable Memory) cell 1 is a defective address memory circuit which can store one bit of a defective address, and includes two floating gate transistors 2 and 3, N-transistors 4 through 7 and P-transistors 8 and 9. Usually, such a memory circuit is called a CAM cell, and a group of CAM cells is called a CAM. The gates of the floating gate transistors 2 and 3 in the CAM cell 1 are commonly connected to a bias voltage generating circuit 10 so that a bias voltage is supplied to the gates of the floating gate transistors 2 and 3. The gates of the N-transistors 4 and 5 are commonly connected to a bias voltage generating circuit 11 so that a bias voltage is supplied to the gates of the N-transistors 4 and 5. A series circuit of the P-transistor 8, the N-transistor 4, and the floating gate transistor 2 is interposed between a Vcc potential and a Vss potential. Similarly, a series circuit of the P-transistor 9, the N-transistor 5, and the floating gate transistor 3 is interposed between the Vcc potential and the Vss potential. The gate of the P-transistor 8 is connected to the junction of the P-transistor 9 and the N-transistor 5, and the gate of the P-transistor 9 is connected to the junction of the P-transistor 8 and the N-transistor 4. The drains of the N-transistors 6 and 7 are commonly connected to an output terminal of a current supply circuit 12, and the gates of the N-transistors 6 and 7 are connected to a decoder circuit 13. The source of the N-transistor 6 is connected to the junction of the floating gate transistor 2 and the N-transistor 4, and the source of the N-transistor 7 is connected to the junction of the floating gate transistor 3 and the N-transistor 5. A plurality of CAM cells 1 (for example, n CAM cells 1-1 to 1-n as indicated in FIG. 7) each having the above-mentioned configuration are arranged. Each of the CAM cells outputs data from an output N4 which is a junction of the P-transistor 9 and the N-transistor 5.
Hereinafter, the operation of the above-mentioned configuration will be described.
First, a method of storing a defective address in the memory circuit 1 will be described. As an example, the case where "0" is stored (programmed) in the CAM cell 1 (N4="0") will be described.
All the floating gate memory cells in the CAM cell 1 have been subjected to the UV erasing (ultraviolet light erasing) so that the threshold voltage (hereinafter, referred to as Vth) is neutralized to be about 2 to 3 V. Generally, the bias voltage generating circuits 10 and 11 output an intermediate potential and a Vcc potential, respectively. When the programming is to be done, the output N10 of the bias voltage generating circuit 10 is set to be a high voltage of 10 V or higher, and the bias voltage of the output N11 of the bias voltage generating circuit 11 is lowered to the Vss level, so that the N-transistors 4 and 5 are turned off, resulting in that only an output N13-1a among the outputs of the decoder 13 is raised to about 7 to 8 V. An output N13-1b of the decoder 13 is used only during another programming.
Under this state, during a given period, an output N12 of the current supply circuit 12 is raised to a high voltage of about 10 to 12 V. In this case, the transistor 7 is turned off and only the transistor 6 is turned on. Therefore, a voltage of about 6 to 7 V is applied via the transistor 6 to the output N1 in the drain side of the floating gate transistor 2, and a current flows between the drain and source of the floating gate transistor 2. Hot electrons generated by the current are caused to be injected into the floating gate of the transistor 2, by the output N10 which functions as the bias voltage applied to the transistor 2, thereby raising the Vth of the transistor 2. The Vth is raised to a level approximately equal to or higher than the Vcc potential. The Vth of the transistor 3 remains to be neutralized to be about 2 to 3 V. In this way, the difference of the Vth levels of the transistors 2 and 3 causes "0" to be stored in the CAM cell 1. The above is strictly identical with the writing process of a usual hot electron injection EPROM or flash memory.
Next, the case where "1" is stored (programmed) in the CAM cell 1 (N4="H") will be described.
Only an output N13-1b of the decoder 13 is set to be higher than the Vcc potential. Under this state, during a given period, the output N12 of the current supply circuit 12 is raised to a high voltage of about 10 to 12 V. In this case, the transistor 6 is turned off and only the transistor 7 is turned on. Therefore, a voltage of about 6 to 7 V is applied via the transistor 7 to the node N2 in the drain side of the floating gate transistor 3, and a current flows between the drain and source of the floating gate transistor 3. Thus, in the same manner as described above, the Vth of the transistor 3 is raised. The Vth of the transistor 2 remains to be neutralized to be about 2 to 3 V. In this way, the difference of the Vth levels of the transistors 2 and 3 causes "1" to be stored in the CAM cell 1.
The above-mentioned operations are conducted on all the CAM cells 1 in the CAM before shipment of the device, so that "0" or "1" is respectively stored (programmed) in each of the CAM cells.
Next, the case where a device shipped after the programming described above is used by the user will be described. It is assumed that, in this case, "0" (N4="L") is stored (programmed) in the CAM cell 1.
When the device is powered on, the output N10 of the bias potential is set to be the Vcc potential and the output N11 of the bias potential is raised to a potential which is approximately twice (about 2 V) the threshold voltage of the transistors 4 and 5, whereby the transistors 4 and 5 are made turned on. At this time, the output N10 which functions as the gate potential of the transistors 2 and 3 is at the Vcc potential, which is at an intermediate level higher than the Vth of the transistor 3 and lower than that of the transistor 2. Thus, the transistor 3 allows a current to pass therethrough and the transistor 2 is turned off. Therefore, the output N4 is pulled down to the "L" level by the transistors 3 and 5. The output N4 is connected to the gate of the transistor 8. When the output N4 is lowered to the "L" level, therefore, the transistor 8 is turned on. Since the transistor 2 is turned off, however, the output N3 is completely pulled up to the Vcc level. The pull-up of the output N3 to the Vcc level causes the transistor 9 which uses the output as the gate potential, to become turned off so that the output N4 is completely set to the Vss level. In this state, the outputs N3 and N4 are completely set to the Vcc and Vss levels, respectively, and hence a DC current cannot flow any longer. As a result, "0" (N4="L") is output from the output N4.
In the case where "1" (N4="H") is to be output from the output N4, the relationship between the Vth levels of the transistors 2 and 3 is inverted, and the subsequent operations are the same as those described above.
In the above, the operation of the CAM cell 1 has been described. After the device is powered on, the CAM cell 1 is latched to this state. All the other CAM cells 1 are latched in the same manner, and "1" or "0" is output from the respective outputs N4.
The conventional CAM cells 1 described above have the following problems.
In U.S. Pat. No. 5,267,213, the improved bias voltage generating circuit 11 has a configuration shown in FIG. 8. In the circuit, a current to be consumed can be reduced in level, and the period to be elapsed until the output reaches a specified value can be shortened. Actually, however, a minute DC current must flow through a series circuit of the transistors 14 and 15 in order to obtain a stable output voltage. When such a supply of a DC current is to be completely eliminated, a power-down signal must externally be supplied to power off the circuit. However, this countermeasure has a drawback that, when the circuit is next powered on, the operations of the transistors, etc. require a short period to be elapsed until the output reaches the specified value, resulting in that the access time is prolonged in the case of a memory.
Another problem is as follows: In the CAM cell 1, when the Vcc potential exceeds the Vth of the floating gate transistor 2 (the transistor having a higher Vth) which is programmed so as to be raised, or, for example, when Vcc=5.5 V and Vth=5.3 V, the potential of the output N10 of the bias voltage generating circuit 10 becomes Vcc, and hence the transistor 2 which should be turned off is turned on. At this time, since the transistor 3 is turned on and the output N4 is at the L level, the transistor 8 is turned on. Since the transistor 4 is originally turned on, a DC current flows from the Vcc potential to the Vss potential through the series circuit of the transistors 8, 4 and 2. Although each DC current flowing through the respective CAM cell 1 is very low in level, the use of plural CAM cells 1 in the whole of device causes the DC currents to be accumulated, and the resulting DC current level is so large that the stand-by current of the device is adversely affected.
In a countermeasure of preventing a DC current from flowing even in the case where the Vcc potential is high, the Vth of a floating gate transistor to be programmed is set to be high. In order to conduct the countermeasure, however, the output N10 of the bias voltage must be set to be high during the process of programming the CAM cell 1. This produces problems of dielectric strength and reliability of the transistors 2 and 3.
Another countermeasure may be considered in which the potential of the output N10 is always set to be lower than the Vcc potential by a fixed voltage. However, the provision of a circuit which always sets the output to be lower than the Vcc potential by the fixed voltage produces the following problem. When the Vcc potential is lowered, or, for example, when the output N10 of the bias voltage is set to be lower than the Vcc potential by 1 V and the Vcc potential is lowered to about 3 V, the potential of the output N10 becomes about 2 V. Then, the transistor 3 which must usually be turned on becomes turned off because the Vth of the transistor is about 2 to 3 V, with the result that the CAM cell can no longer correctly operate.
It may be possible to design a circuit which can lower the voltage of the output N10 only when the Vcc potential is high. However, this involves an addition of a further bias voltage generating circuit which naturally consumes a large current. Since such a circuit itself consumes a DC current, the circuit hinders the original object of reducing the stand-by current to a level as low as possible.
In other words, when a such a CAM circuit is used for holding (latching) data (addresses), a conventional system requires the holding portion to be kept activated during the process of outputting the stored (programmed) data. Accordingly, the bias voltage generating circuits 10 and 11 for the holding circuit must always be turned on. The turn-on operation of the bias voltage generating circuits produces a problem in that a current is consumed, and requires a prolonged period when, in the process of reading out the data, the bias voltage generating circuits 10 and 11 are first turned on so that the data is determined by the holding circuit.